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| FINAL AmC0XXDFLKA 4, 8, 20, or 32 Megabyte 5.0 Volt-only Flash Memory PC Card DISTINCTIVE CHARACTERISTICS s High performance -- 150 ns maximum access time s Single supply operation -- Write and erase voltage, 5.0 V 5% -- Read voltage, 5.0 V 5% s CMOS low power consumption -- 45 mA maximum active read current (x8 mode) -- 65 mA maximum active write/erase current (x8 mode) s High write endurance -- Minimum 100,000 program/erase cycles per sector -- 1,000,000 typical program/erase cycles per card s PCMCIA/JEIDA 68-pin standard -- Selectable byte-/or word-wide configuration s Write protect switch -- Prevents accidental data loss s Zero data retention power -- Batteries not required for data storage s Enhanced power management for standby mode -- 1 A typical standby current -- Standard access time from standby mode s Separate attribute memory s Automated write and erase operations increase system write performance -- 64K byte memory sectors for faster automated erase speed -- Typically 1 s per single memory sector erase -- Random address writes to previously erased bytes (8 s typical per byte) s Total system integration solution -- Support from independent software and hardware vendors s Low insertion and removal force -- State-of-the-art connector allows for minimum card insertion and removal effort s Erase Suspend/Resume -- Supports reading or programming data to a sector not being erased within the same device s Support for RY/BY and RESET signals GENERAL DESCRIPTION AMD's 5.0 Volt-only Flash Memory PC Card provides the highest system level performance for data and file storage solutions to the portable PC market segment and a wide range of embedded applications. Manufactured with AMD's Negative Gate Erase, 5.0 Volt-only technology, the AMD 5.0 Volt-only Flash Memory Cards are the most cost-effective and reliable approach to single-supply Flash memory cards. Data files and application programs can be stored on the D-Series cards. This allows OEM manufacturers of portable systems to eliminate the weight, high-power consumption and reliability issues associated with electro-mechanical disk-based systems. The D-Series cards also allow today's bulky and heavy battery packs to be reduced in weight and size. AMD's Flash Memory PC Cards provide the most efficient method to transfer useful work between different hardware platforms. The enabling technology of the D-Series cards enhances the productivity of mobile workers. Widespread acceptance of the D-Series cards is assured due to their compatibility with the 68-pin PCMCIA/JEIDA international standard. AMD's Flash Memory Cards can be read in either a byte-wide or word-wide mode which allows for flexible integration into various system platforms. Compatibility is assured at the hardware interface and software interchange specification. The Card Information Structure (CIS) or Metaformat, can be written by the OEM into the memory card's attribute memory address space beginning at address 00000H by using a format utility. The CIS appears at the beginning of the Card's attribute memory space and defines the low-level organization of data on the PC Card. The D-Series cards contains a separate EEPROM memory for the cards' attribute memory space. This allows all of the Flash memory to be used for the common memory space. Third party software solutions such as Microsoft's and SystemSoft's Flash File System (FFS2), SCM's SCM-FTL, and Datalight's Cardtrick enable AMD's Flash Memory PC Card to replicate the function of traditional disk-based memory systems. Publication# 19521 Rev: D Amendment/0 Issue Date: December 1996 BLOCK DIAGRAM Write Protect Switch VCC 10K R D0-D15 I/O WE Transceivers OE and Buffers 10K VCC D8-D15 D0-D7 WP RY/BY (Output) VCC 3.3K A0 A0-A24 VCC R R R A1-A24 CE2 CE1 A1-A9 Address Buffers and Decoders A1-A21 IWEH IOEH IWEL IOEL ICE0 ICE1 A0 CE2 CE1 REG Decoder ICE7 Am29F016C A0-A8 D0-D7 Attribute Memory CE A0-A20 D0-D7 CE WE S0* OE RY/BY VSS VCC RST Am29F016C A0-A20 D8-D15 CE WE S1* OE RY/BY VSS VCC RST CD1 CD2 A0-A20 D0-D7 CE WE S2* OE RY/BY VSS VCC RST A0-A20 D8-D15 CE WE S3* OE RY/BY VSS VCC RST Card Detect A0-A20 D0-D7 CE WE S14* OE RY/BY VSS VCC RST GND VCC RESET R A0-A20 D8-D15 CE WE S15* OE RY/BY VSS VCC RST 19521D-1 Notes: R = 20 K(min)/140 K (max) *4 Mbyte card = S0 + S1, 8 Mbyte card = S0...S3, 20 Mbyte card = S0...S9, 32 Mbyte card = S0...S15 2 AmC0XXDFLKA PC CARD PIN ASSIGNMENTS Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE RY/BY VCC1 NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND I I I I I I I I I I I I/O I/O I/O O I/O I/O I/O I/O I/O I I I I I I I I I I/O Ground Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Card Enable 1 (Note 3) Address Bit 10 Output Enable Address Bit 11 Address Bit 9 Address Bit 8 Address Bit 13 Address Bit 14 Write Enable Ready/Busy Power Supply No Connect (Note 1) Address Bit 16 Address Bit 15 Address Bit 12 Address Bit 7 Address Bit 6 Address Bit 5 Address Bit 4 Address Bit 3 Address Bit 2 Address Bit 1 Address Bit 0 Data Bit 0 Data Bit 1 Data Bit 2 Write Protect (Note 3) Ground Function Pin# 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Signal GND CD1 D11 D12 D13 D14 D15 CE2 NC NC NC A17 A18 A19 A20 A21 VCC2 NC A22 A23 A24 NC NC RESET NC NC REG BVD2 BVD1 D8 D9 D10 CD2 GND I O O I/O I/O I/O O I I I I I I I I O I/O I/O I/O I/O I/O I I/O Ground Card Detect 1 (Note 3) Data Bit 11 Data Bit 12 Data Bit 13 Data Bit 14 Data Bit 15 Card Enable 2 (Note 3) No Connect No Connect No Connect Address Bit 17 Address Bit 18 Address Bit 19 Address Bit 20 Address Bit 21 Power Supply No Connect (Note 1) Address Bit 22 Address Bit 23 Address Bit 24 No Connect No Connect RESET No Connect No Connect Register Select Battery Vltg Detect 2 (Note 2) Battery Vltg Detect 1 (Note 2) Data Bit 8 Data Bit 9 Data Bit 10 Card Detect 2 (Note 3) Ground Function Notes: I = Input to card, O = Output from card I/O = Bidirectional NC = No connect In systems which switch VCC individually to cards, no signal should be directly connected between cards other than ground. 1. VPP not required for Programming or Reading operations. 2. BVD = Internally pulled-up. 3. Signal must not be connected between cards. AmC0XXDFLKA 3 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM C 0XX D FL K A CSxxxxx CUSTOMER SPECIFIC IDENTIFICATION NUMBER REVISION LEVEL OUTPUT CONFIGURATION: (x16/x8) FLASH TECHNOLOGY 5.0 Volt-only OPERATION WITH 100,000 ERASE/PROGRAM CYCLES MINIMUM MEMORY CARD DENSITY 004 = Four Megabytes 008 = Eight Megabytes 020 = Twenty Megabytes 032 = Thirty-two Megabytes PC MEMORY CARD AMD 4 AmC0XXDFLKA Differences Between the D-Series and C-Series Cards The differences between the D-Series Card and the earlier C-Series Cards are as follows: s The D-Series Cards are based on AMD's latest 16 MBit 5.0 Volt-only device, the Am29F016C. The earlier C-Series Cards were based on the 4 MBit 5.0 Volt-only device, the Am29F040. s The D-Series Cards program faster than the CSeries Cards. This is due to faster byte write times and an optimized address unlock sequence for write operations. s The D-Series Cards are offered in higher densities. The D-Series Cards are available in densities of 4 MBytes, 8 MBytes, 20 MBytes, and 32 MBytes. The earlier C-Series Cards were available in densities of 1 MByte, 2 MBytes, 4 MBytes and 10 MBytes. The additional features that are supported in the new D-Series Cards include s The D-Series Cards support the RESET feature. This allows you to asynchronously RESET the Card into the read state. s The D-Series Cards also provide the RY/BY functionality. This feature provides a quick way of determining if the Card is busy doing a write or erase operation, or if it is in a position to undertake the next operation. s Availability of an additional Toggle bit (D2) to determine if the Card is in the Embedded Erase or Erase Suspend mode. s Programming operations can be executed in 8 s pulses, down from the 16 s on the C-Series Cards (typical). s Time out from the rising edge of the WE pulse for sector erase command reduced from 100 s to 50 s. s The D-Series Cards offers a low power standby mode with fast recovery time to read. The typical standby current (ICCS) is <1 A with recovery at standard read access time. AmC0XXDFLKA 5 PIN DESCRIPTION A0-A24 Address Inputs These inputs are internally latched during write cycles. All address lines should be driven. RESET This input to the Card is used to reset all the Flash devices inside the Card to a read mode state. If you drive or assert RESET high during a write or erase operation, then the state of the devices for the purpose of the operation is undefined. In order to RESET, you need to hold the RESET pin high for 500 ns, and it takes 20 s before the internal circuit is RESET. When RESET is driven high, the data bus is in a high impedance state. BVD1, BVD2 Battery Voltage Detect Internally pulled-up. VCC PC Card Power Supply For device operation (5.0 V 5%). CD1, CD2 Card Detect When card detect 1 and 2 = ground the system detects the card. WE Write Enable This input is active low and controls the write function of the command register to the memory array. The target address is latched on the falling edge of the WE pulse and the appropriate data is latched on the rising edge of the pulse. CE1, CE2 Card Enable This input is active low. The memory card is deselected and power consumption is reduced to standby levels when CE is high. CE activates the internal memory card circuitry that controls the high and low byte control logic of the card, input buffers segment decoders, and associated memory devices. WP Write Protect This output is active high and disables all Card write operations (including writes to the attribute memory). D0-D15 Data Input/Output Data inputs are internally latched on write cycles. Data outputs during read cycles. Data pins are active high. When the memory card is deselected or the outputs are disabled the outputs float to tristate. MEMORY CARD OPERATIONS The D-Series Flash Memory Card is organized as an array of individual devices. Each device is 2 Mbytes in size with thirty-two 64K byte sectors. Although the address space is continuous, each physical device defines a logical address segment size. Erase operations can be performed on two 64KByte sectors simultaneously. Once a memory sector or memory segment is erased any address location may be programmed. Flash technology allows any logical "1" data bit to be programmed to a logical "0". The only way to reset bits to a logical "1" is to erase the entire memory sector of 64K bytes or memory segment of 2 Mbytes. Erase operations are the only operations that work on entire memory sectors or memory segments. All other operations such as word-wide programming are not affected by the physical memory segments. The common memory space data contents are altered in a similar manner as writing to individual Flash memory devices. On-card address and data buffers activate the appropriate Flash device in the memory array. Each device internally latches address and data during write cycles. Refer to Table 1. Attribute memory is a separately accessed card memory space. The attribute memory space is active when the REG pin is driven low. The Card Information Structure (CIS) describes the capabilities and specification GND Ground NC No Connect Corresponding pin is not connected. OE Output Enable This input is active low and enables the data buffers through the card outputs during read cycles. RY/BY This signal is output from the card and indicates the status of the operation in progress in the card. If this signal is low, then the card is still busy with the current operation. Otherwise, the card is ready to accept anew operation. REG Attribute Memory Select This input is active low and enables reading the CIS from the EEPROM. 6 AmC0XXDFLKA of a card. The CIS is stored in the attribute memory space beginning at address 00000H. The D-Series cards contain a separate EEPROM for the Card Information Structure. D0-D7 are active during attribute memory accesses. D8-D15 should be ignored. Odd order bytes present invalid data. Refer to Table 2. Table 1. Function Read Mode Standby Mode Word Access Low Byte Access Odd Byte Access Odd-Byte-Only Access Write Mode Standby Mode Word Access (Note 3) Even Byte Access (Note 4) Odd Byte Access (Note 4) Odd-Byte-Only Access (Note 4) Output Disable X H Word-Wide Operations The D-Series cards provide the flexibility to operate on data in a byte-wide or word-wide format. In word-wide operations the CE1 and CE2 must be low and A0 is not used for any addressing. Common Memory Bus Operations CE2 CE1 OE WE A0 D8-D15 D0-D7 REG X H H H H H L H H L H L L L H X L L L L X H H H H X X L H X High-Z Data Out-Odd High-Z High-Z Data Out-Odd High-Z Data Out-Even Data Out-Even Data Out-Odd High-Z H L H H L X H L L L H X X H H H H H X L L L L H X X L H X X X Data In-Odd High-Z High-Z Data In-Odd High-Z X Data In-Even Data In-Even Data In-Odd High-Z High-Z H H H H Notes: 1. X indicates a don't care value. 2. VPP pins are not connected in the 5.0 Volt-only Flash Memory Card. 3. Refer to Table 5 for valid DIN during a word write operation. 4. Refer to Table 3 and 4 for valid DIN during a byte write operation. 5. During odd byte access, A0 = VIH outputs or inputs the "odd" byte (high byte) of the x16 word on D0-D7. This is accomplished internal to the card by transposing D8-D15 to D0-D7. 6. During odd-byte-only access , A0 = X outputs or inputs the "odd" byte (high byte) of the x16 word on D8-D15. AmC0XXDFLKA 7 Table 2. Pins/Operation READ/WRITE Read Mode (Note 3) Standby Mode Word Access (Note 4) Even Byte Access Odd Byte Access (Note 4) Odd-Byte-Only Access (Note 4) Write Mode (Note 5,6) Standby Mode Word Access Low Byte Access Odd Byte Access Odd-Byte-Only Access Output Disable X L L L L L X L L L L REG Attribute Memory Bus Operations CE2 CE1 OE WE A0 D8-D15 D0-D7 H L H H L H L L L H X L L L L X H H H H X X L H X High-Z Not Valid High-Z High-Z Not Valid High-Z Data Out-Even Data Out-Even Not Valid High-Z H L H H L X H L L L H X X H H H X H X L L L H H X X L H L X X X X X X High-Z X Data In-Even Data In-Even X X High-Z Notes: 1. X indicates any value. 2. VPP pins are not connected in the 5.0 Volt-Only Flash Memory Card. 3. During Attribute Memory Read function, REG and OE must be active for the entire cycle. 4. Only even-byte data is valid during Attribute Memory Read function. 5. During Attribute Memory Write function, REG and WE must be active for the entire cycle, OE must be inactive for the entire cycle. 6. The first 128 bytes of the attribute memory is not writable as it contains the CIS. Only the remaining 384 bytes are writable. 8 AmC0XXDFLKA Byte-Wide Operations Byte-wide data is available on D0-D7 for read and write operations (CE1 = low, CE2 = high). Even and odd bytes are stored in separate memory segments (i.e., S0 and S1) and are accessed when A0 is low and high respectively. The even byte is the low order byte and the odd byte is the high order byte of a 16-bit word. Erase operations in the byte-wide mode must account for data multiplexing on D0-D7 by changing the state of A0. Each memory sector or memory segment pair must be addressed separately for erase operations. Read Characteristics and Waveforms for the specific timing parameters. Output Disable Data outputs from the card are disabled when OE is at a logic-high level. Under this condition, outputs are in the high-impedance state. Standby Operations Byte-wide read accesses only require half of the read/ write output buffer (x16) to be active. In addition, only one memory segment is active within either the high order or low order bank. Activation of the appropriate half of the output buffer is controlled by the combination of both CE pins. The CE pins also control power to the high and low-order banks of memory. Outputs of the memory bank not selected are placed in the high impedance state. The individual memory segment is activated by the address decoders. The other memory segments operate in standby. An active memory segment continues to draw power until completion of a write or erase operation if the card is deselected in the process of one of these operations. Card Detection Each CD (output) pin should be read by the host system to determine if the memory card is adequately seated in the socket. CD1 and CD2 are internally tied to ground. If both bits are not detected, the system should indicate that the card must be reinserted. Write Protection The AMD Flash memory card has three types of write protection. The PCMCIA/JEIDA socket itself provides the first type of write protection. Power supply and control pins have specific pin lengths in order to protect the card with proper power supply sequencing in the case of hot insertion and removal. A mechanical write protect switch provides a second type of write protection. When this switch is activated, WE is internally forced high. The Flash memory command register is disabled from accepting any write commands. The third type of write protection is achieved with VCC1 and VCC2 below 3.2 V VLKO. Each Flash memory device that comprises a Flash memory segment will reset the command register to the read-only mode when VCC is below VLKO. VLKO is the voltage below which write operations to individual command registers are disabled. Auto Select Operation A host system or external card reader/writer can determine the on-card manufacturer and device I.D. codes. Codes are available after writing the 90H command to the command register of a memory segment per Tables 3 and 4. Reading from address location 00000H in any segment provides the manufacturer I.D. while address location 00002H provides the device I.D. To terminate the Auto Select operation, it is necessary to write the Read/Reset command sequence into the register. Write Operations Write and erase operations are valid only when VCC1 and VCC2 are above 4.75 V. This activates the state machine of an addressed memory segment. The command register is a latch which saves address, commands, and data information used by the state machine and memory array. When Write Enable (WE) and appropriate CE(s) are at a logic-level low, and Output Enable (OE) is at a logic-high, the command register is enabled for write operations. The falling edge of WE latches address information and the rising edge latches data/command information. Write or erase operations are performed by writing appropriate data patterns to the command register of accessed Flash memory sectors or memory segments. The byte-wide and word-wide commands are defined in Tables 3, 4, and 5, respectively. MEMORY CARD BUS OPERATIONS Read Enable Two Card Enable (CE) pins are available on the memory card. Both CE pins must be active low for word-wide read accesses. Only one CE is required for byte-wide accesses. The CE pins control the selection and gates power to the high and low memory segments. The Output Enable (OE) controls gating accessed data from the memory segment outputs. The device will automatically power-up in the read/ reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC AmC0XXDFLKA 9 Table 3. Embedded Command Sequence Reset/Read Reset/Read Autoselect Byte Write Segment Erase Sector Erase Bus Write Cycles Req'd 1 4 4 4 6 6 First Bus Write Cycle Addr* XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH Data F0 AA AA AA AA AA B0 30 Even Byte Command Definitions (Note 5) Second Bus Write Cycle Addr* Data Third Bus Write Cycle Addr* Data Fourth Bus Read/Write Cycle Addr* Data Fifth Bus Write Cycle Addr* Data Sixth Bus Write Cycle Addr* Data XXXXH XXXXH XXXXH XXXXH XXXXH 55 55 55 55 55 XXXXH XXXXH XXXXH XXXXH XXXXH F0 90 RA 00H 02H RD 01 3D PD AA AA XXXXH XXXXH 55 55 XXXXH SA 10 30 A0 80 80 PA XXXXH XXXXH Sector Erase Suspend Sector Erase Resume Erase can be suspended during sector erase with Addr (don't care), Data (B0H) Erase can be resumed after suspend with Addr (don't care), Data (30H) * Address for Memory Segment 0 (S0) only. Address for the higher even memory segments (S2-S14) = (Addr) + (N/2)* 400000H where N = Memory Segment number (0) for 4 Mbyte, N = (0, 2) for 8 Mbyte, N = (0, 2, 4) for 12 Mbyte, N = (0...8) for 20 Mbyte, N = (0...14) for 32 Mbyte. Notes: 1. Address bits = X = Don't Care for all address commands except for Program Address (PA), Read Address (RA) and Sector Address (SA). 2. Bus operations are defined in Table 1. 3. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A17, A18, A19, A20, A21 will uniquely select any sector of a segment. To select the memory segment: 4 Mbyte: Use CE1 8 Mbyte: Use CE1 and A22 20 and 32 Mbyte: Use CE1 and A22-A24. 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE pulse. 5. A0 = 0 and CE1 = 0. 10 AmC0XXDFLKA Table 4. Embedded Command Sequence Reset/Read Reset/Read Autoselect Byte Write Segment Erase Sector Erase Bus Write Cycles Req'd 1 4 4 4 6 6 First Bus Write Cycle Addr* XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH Data F0 AA AA AA AA AA AA AA Odd Byte Command Definitions (Notes 1-5) Second Bus Write Cycle Addr* Data Third Bus Write Cycle Addr* Data Fourth Bus Read/Write Cycle Addr* Data Fifth Bus Write Cycle Addr* Data Sixth Bus Write Cycle Addr* Data XXXXH XXXXH XXXXH XXXXH XXXXH 55 55 55 55 55 XXXXH XXXXH XXXXH XXXXH XXXXH F0 90 RA 00H 02H RD 01 3D PD AA AA XXXXH XXXXH 55 55 XXXXH SA 10 30 A0 80 80 PA XXXXH XXXXH Sector Erase Suspend Sector Erase Resume Erase can be suspended during sector erase with Addr (don't care), Data (B0H) Erase can be resumed after suspend with Addr (don't care), Data (30H) * Address for Memory Segment 1 (S1) only. Address for the higher odd memory segments (S3-S15) = (Addr) + ((N-1)/2)* 400000H + 20000H where N = Memory Segment number (1) for 4 Mbyte, N = (1, 3) for 8 Mbyte, N = (1, 3, 5) for 12 Mbyte, N = (1...9) for 20 Mbyte, N = (1...15) for 32 Mbyte. Notes: 1. Address bits = X = Don't Care for all address commands except for Program Address (PA), Read Address (RA) and Sector Address (SA). 2. Bus operations are defined in Table 1. 3. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A17, A18, A19, A20, A21 will uniquely select any sector of a segment. To select the memory segment: 4 Mbyte: Use CE2 8 Mbyte: Use CE2 and A22 20 and 32 Mbyte: Use CE2 and A22-A24. 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE pulse. 5. A0 = 1 and CE1 = 0 or A0 = X and CE2 = 0. AmC0XXDFLKA 11 Table 5. Embedded Command Sequence Reset/Read Reset/Read Autoselect Byte Write Segment Erase Sector Erase Bus Write Cycles Req'd 1 4 4 4 6 6 First Bus Write Cycle Addr* Data Word Command Definitions (Notes 1-7) Second Bus Write Cycle Addr* Data Third Bus Write Cycle Addr* Data Fourth Bus Read/Write Cycle Addr* Data Fifth Bus Write Cycle Addr* Data Sixth Bus Write Cycle Addr* Data XXXXH F0F0 XXXXH AAAA XXXXH 5555 XXXXH XXXXH AAAA XXXXH 5555 XXXXH F0 90 02H XXXXH AAAA XXXXH 5555 XXXXH A0A0 XXXXH AAAA XXXXH 5555 XXXXH 8080 XXXXH AAAA XXXXH 5555 XXXXH 8080 PA XXXXH XXXXH 3D3D PW AAAA AAAA 5554H 5555 XXXXH 1010 5554H 5555 SA 3030 RA 00H RW 0101 Sector Erase Suspend Sector Erase Resume XXXXH B0B0 Erase can be suspended during sector erase with Addr (don't care), Data (B0B0H) XXXXH 3030 Erase can be resumed after suspend with Addr (don't care), Data (3030H) Notes: 1. Address bits = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA). 2. Bus operations are defined in Table 1. 3. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A17, A18, A19, A20, A21will uniquely select any sector of a segment. To select the memory segment: 4 Mbyte: Use CE1, CE2 8 Mbyte: Use CE1, CE2 20 and 32 Mbyte: Use CE1, CE2, A22-A24. 4. RW = Data read from location RA during read operation. (Word Mode). PW = Data to be programmed at location PA. Data is latched on the rising edge of WE. (Word Mode). 5. Address for Memory Segment Pair 0 (S0 and S1) only. Address for the higher Memory Segment Pairs (S2, S3 = Pair 1; S4, S5 = Pair 2; S6, S7 = Pair 3...) is equal to (Addr) + M* (40000H) where M = Memory Segment Pair number. 6. Word = 2 bytes = odd byte and even byte. 7. CE1 = 0 and CE2 = 0. 12 AmC0XXDFLKA FLASH MEMORY PROGRAM/ERASE OPERATIONS Details of AMD's Embedded Write and Erase Operations Embedded Erase Algorithm The automatic memory sector or memory segment erase does not require the device to be entirely pre-programmed prior to executing the Embedded Erase command. Upon executing the Embedded Erase command sequence, the addressed memory sector or memory segment will automatically write and verify the entire memory segment or memory sector for an all "zero" data pattern. The system is not required to provide any controls or timing during these operations. When the memory sector or memory segment is automatically verified to contain an all "zero" pattern, a self-timed chip erase-and-verify begins. The erase and verify operations are complete when the data on D7 (D15 on the odd byte) of the memory sector or memory segment is "1" (see Write Operation Status section) at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. A Reset command after the device has begun execution will stop the device but the data in the operated segment will be undefined. In that case, restart the erase on that sector and allow it to complete. When using the Embedded Erase algorithm, the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). The margin voltages are internally generated in the same manner as when the standard erase verify command is used. The Embedded Erase command sequence is a command only operation that stages the memory sector or memory segment for automatic electrical erasure of all bytes in the array. The automatic erase begins on the rising edge of the WE and terminates when the data on D7 of the memory sector or memory segment is "1" (see Write Operation Status section) at which time the device returns to the Read mode. Please note that for the memory segment or memory sector erase operation, Data Polling may be performed at any address in that segment or sector. Figure 1 and Table 6 illustrate the Embedded Erase Algorithm, a typical command string and bus operations. As described earlier, once the memory sector in a device or memory segment completes the Embedded Erase operation it returns to the Read mode and addresses are no longer latched. Therefore, the device requires that the address of the sector being erased is supplied by the system at this particular instant of time. Otherwise, the system will never read a "1" on D7. A Table 6. Bus Operation Standby Write Read Embedded Erase Algorithm Command Comments Wait for VCC ramp Embedded Erase command sequence 6 bus cycle operation Data Polling to verify erasure system designer has two choices to implement the Embedded Erase algorithm: 1. The system (CPU) keeps the sector address (within any of the sectors being erased) valid during the entire Embedded Erase operation, or 2. Once the system executes the Embedded Erase command sequence, the CPU takes away the address from the device and becomes free to do other tasks. In this case, the CPU is required to keep track of the valid sector address by loading it into a temporary register. When the CPU comes back for performing Data Polling, it should reassert the same address. Since the Embedded Erase operation takes a significant amount of time (1 s-30 s), option 2 makes more sense. However, the choice of these two options has been left to the system designer. Figure 1 and Table 6 illustrate the Embedded Erase Algorithm, a typical command string and bus operations. Sector Erase Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set up" command. Two more "unlock" write cycles are then followed by the sector erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command (data) is latched on the rising edge of WE. A time-out of 50 s from the rising edge of the last sector erase command will initiate the sector erase command(s). Multiple sectors may be erased by writing the six bus cycle operations as described above. This sequence is followed with writes of the sector erase command 30H to addresses in other sectors to be erased. A time-out of 50 s from the rising edge of the WE pulse for the last sector erase command will initiate the sector erase. If another sector erase command is written within the 50 s time-out window the timer is reset. Any command other than sector erase within the time-out window will reset the device to the read mode, ignoring the previous command string (refer to Write Operation Status section for Sector Erase Timer operation). Loading the sector erase buffer may be done in any sequence and with anysector number. AmC0XXDFLKA 13 Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations to "0" in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. A Reset command after the device has begun execution will stop the device but the data in the operated sector will be undefined. In that case, restart the erase on that sector and allow it to complete. The automatic sector erase begins after the 50 s time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on D7 is "1" (see Write Operation Status section) at which time the device returns to read mode. Data Polling must be performed at an address within any of the sectors being erased. Figure 1 illustrates the Embedded Erase Algorithm using typical command strings and bus operations. to this bit (see Write Operation Status section) at which time the device returns to the Read mode (no write verify command is required). Addresses are latched on the falling edge of WE during the Embedded Program command execution and hence the system is not required to keep the addresses stable during the entire Programming operation. However, once the device completes the Embedded Program operation, it returns to the Read mode and addresses are no longer latched. Therefore, the device requires that a valid address input to the device is supplied by the system at this particular instant of time. Otherwise, the system will never read a valid data on D7. A system designer has two choices to implement the Embedded Programming algorithm: 1. The system (CPU) keeps the address valid during the entire Embedded Programming operation, or 2. Once the system executes the Embedded Programming command sequence, the CPU takes away the address from the device and becomes free to do other tasks. In this case, the CPU is required to keep track of the valid address by loading it into a temporary register. When the CPU comes back for performing Data Polling, it should reassert the same address. However, since the Embedded Programming operation takes only 8 s typically, it may be easier for the CPU to keep the address stable during the entire Embedded Programming operation instead of reasserting the valid address during Data Polling. Anyway, this has been left to the system designer's choice to go for either operation. Any commands written to the segment during this period will be ignored. Figure 2 and Table 7 illustrate the Embedded Program Algorithm, a typical command string, and bus operation. Table 7. Bus Operation Start Write Embedded Erase Command Sequence (Table 3 and 4) Data Poll from Device (Figure 3) Erasure Complete 19521D-2 Figure 1. Embedded Erase Algorithm Embedded Program Algorithm Command Comments Wait for VCC ramp Embedded Program command sequence Program Address/ Data 3 bus cycle operation 1 bus cycle operation Data Polling to verify program Embedded Program Algorithm The Embedded Program setup is a four bus cycle operation that stages the addressed memory sector or memory segment for automatic programming. Once the Embedded Program setup operation is performed, the next WE pulse causes a transition to an active programming operation. Addresses are internally latched on the falling edge of the WE pulse. Data is internally latched on the rising edge of the WE pulse. The rising edge of WE also begins the programming operation. The system is not required to provide further control or timing. The device will automatically provide an adequate internally generated write pulse and verify margin. The automatic programming operation is completed when the data on D7 of the addressed memory sector or memory segment is equivalent to data written 14 Standby Write Write Read Reset Command The Reset command initializes the sector or segment to the read mode. Please refer to Tables 3 and 4, "Byte Command Definitions," and Table 5, "Word Command Definitions" for the Reset command operation. The sector or segment remains enabled for reads until the command register contents are altered. AmC0XXDFLKA Start Write Embedded Write Command Sequence per Table 3 or 4 Data Poll Device Verify Byte Yes No Last Address Yes Completed No Increment Address 19521D-3 Figure 2. Embedded Programming Algorithm in Byte-Wide Mode a busy condition during the RESET pulse. Refer to Figure 21 for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. RY/BY is best used to interrupt the CPU when an erase completes. Polling is best for byte programming. Data Polling--D7 (D15 on Odd Byte) The Flash Memory PC Card features Data Polling as a method to indicate to the host system that the Embedded algorithms are either in progress or completed. While the Embedded Programming algorithm is in operation, an attempt to read the device will produce the complement of expected valid data on D7 of the addressed memory sector or memory segment. Upon completion of the Embedded Program algorithm an attempt to read the device will produce valid data on D7. The Data Polling feature is valid after the rising edge of the fourth WE pulse of the four write pulse sequence. While the Embedded Erase algorithm is in operation, D7 will read "0" until the erase operation is completed. Upon completion of the erase operation, the data on D7 will read "1". The Data Polling feature is only active during the Embedded Programming or Erase algorithms. Please note that the AmC0XXDFLKA data pin (D7) may change asynchronously while Output Enable (OE) is asserted low. This means that the device is driving status information on D7 at one instant of time and then the byte's valid data at the next instant of time. Depending on The Reset command will safely reset the segment memory to the Read mode. Memory contents are not altered. Following any other command, write the Reset command once to the segment. This will safely abort any operation and reset the device to the Read mode. The Reset is needed to terminate the auto select operation. It can be used to terminate an Erase or Sector Erase operation, but the data in the sector or segment being erased would then be undefined. Write Operation Status RY/BY Ready/Busy The D-Series Card provides a RY/BY output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the card is busy with either a program or erase operation. If the output is high, the card is ready to accept any read/write or erase operation. When the RY/BY pin is low, the card will not accept any additional program or erase commands with the exception of the Erase Suspend command to the same device pair, one can still write or erase to a different device pair. If the card is placed in an Erase Suspend mode, the RY/BY output will be high. During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate AmC0XXDFLKA 15 when the system samples the D7 output, it may read either the status or valid data. Even if the device has completed the Embedded operation and D7 has a valid data, the data outputs on D0-D6 may be still invalid since the switching time for data bits (D0-D7) will not be the same. This happens since the internal delay paths for data bits (D0-D7) within the device are different. The valid data will be provided only after a certain time delay ( 16 AmC0XXDFLKA two status bits, along with that of D7, is summarized as follows: Mode Program Erase Erase Suspend Read (Note 1) (Erase-Suspended Sector) Erase Suspend Program D7 D7 0 1 D6 toggles toggles 1 D2 1 toggles toggles erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause D2 to toggle. (See the section on D2). After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Byte Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Byte Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-program mode will cause D2 to toggle. The end of the erase-suspended program operation is detected by the RY/BY output pin, Data Polling of D7, or by the Toggle Bit 1 (D6) which is the same as the regular Byte Program operation. Note that D7 must be read from the byte program address while D6 can be read from any address. Every time a Sector Erase Suspend command followed by an Erase Resume command is written, the internal (pulse) counters are reset. These counters are used to count the number of high voltage pulses the memory cell requires to program or erase. If the count exceeds a certain limit, then the D5 bit will be set (Exceeded Time Limit flag). This resetting of the counters is necessary since the Erase Suspend command can potentially interrupt or disrupt the high voltage pulses. To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of the Resume command at this point will be ignored. Another Sector Erase Suspend command can be written after the chip has resumed erasing. D7 1 toggles (Note 2) (Note 2) Notes: 1. These status flags apply when outputs are read from a sector that has been erase-suspended. 2. These status flags apply when outputs are read from the byte address of the non-erase suspended sector. Sector Erase Suspend Sector Erase Suspend command allows the user to interrupt the chip and then do data reads (or program) from a non-busy sector while it is in the middle of a Sector Erase operation (which may take up to several seconds). This command is applicable ONLY during the Sector Erase operation and will be ignored if written during the Chip Erase or Programming operation. The Erase Suspend command (B0H) will be allowed only during the Sector Erase Operation that will include the sector erase time-out period after the Sector Erase commands (30H). Writing this command during the time-out will result in immediate termination of the time-out period and suspension of the erase operation. Any other command written during the Erase Suspend mode will be ignored except the Erase Resume command. Writing the Erase Resume command resumes the erase operation. The addresses are "don't-cares" when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of 15 s to suspend the erase operation. When the device has entered the erase-suspended mode, the RY/BY output pin and the D7 bit will be at logic "1", and D6 will stop toggling. The user must use the address of the erasing sector for reading D6 and D7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been RESET Hardware Reset The D-Series Card may be reset by driving the RESET pin to VIL. The RESET pin must be kept low (VIL) for at least 500 ns. Any operation in progress will be terminated and the internal state machine will be reset to the read mode 20 s after the RESET pin is driven low. If a hardware reset occurs during a program operation, the data at that particular location will be indeterminate. When the RESET pin is low and the internal reset is complete, the Card goes to standby mode and cannot be accessed. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. Once the RESET pin is taken high, the Card requires 500 ns of wake up time until outputs are valid for read access. AmC0XXDFLKA 17 Write Operation Status Table 8. Status Byte Program in Embedded Program Algorithm Embedded Erase Algorithm Erase Suspend Read (Erase Suspended Sector) Erase Suspended Mode Erase Suspend Read (Non-Erase Suspended Sector) Erase Suspend Program (Non-Erase Suspended Sector) Byte Program in Embedded Program Algorithm Exceeded Time Limits Program/Erase in Embedded Erase Algorithm Erase Suspended Mode Erase Suspend Program (Non-Erase Suspended Sector) Write Operation Status D7 D7 0 1 Data D7 D7 0 D7 D6 Toggle Toggle 1 Data Toggle (Note 2) Toggle Toggle Toggle D5 0 0 0 Data 0 1 1 1 D3 0 1 0 Data 1 0 1 1 D2 1 Toggle Toggle (Note 1) Data 1 (Note 3) 1 N/A N/A In Progress Notes: 1. Performing successive read operations from the erase-suspended sector will cause D2 to toggle. 2. Performing successive read operations from any address will cause D6 to toggle. 3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the D2 bit. However, successive reads from the erase-suspended sector will cause D2 to toggle. 18 AmC0XXDFLKA Start VA = Valid Address Read Byte (D0-D7) Addr = VA VA = Byte addr for Write operation VA = Any segment (sector) address during segment (sector) erase operation Yes D7 = Data? No No D5 = 1? Yes Read Byte (D0-D7) Addr = VA D7 = Data? No Fail Yes Pass 19521D-4 Note: D7 is rechecked even if D5 = 1 because D7 may change simultaneously with D5. Figure 3. Data Polling Algorithm AmC0XXDFLKA 19 Start Read Byte (D0-D7) Addr = VA D6 = Toggle? No Yes No D5 = 1? Yes Read Byte (D0-D7) Addr = VA D6 = Toggle? Yes Fail No Pass 19521D-5 Note: D6 is rechecked even if D5 = 1 because D6 may stop toggling at the same time as D5 changes to "1". Figure 4. Toggle Bit 1 Algorithm 20 AmC0XXDFLKA CE tCH tOE tDF OE tOEH WE tCE * D7 tWHWH 3 or 4 D0-D6 D0-D6 = Invalid D0-D6 Valid Data D7 tOH D7 = Valid Data High-Z 19521D-6 * D7 = Valid Data (The device has completed the Embedded operation.) Figure 5. AC Waveforms for Data Polling During Embedded Algorithm Operations CE tOEH WE OE * Data (D0-D7) D6 = Toggle D6 = Toggle tOE 19521D-7 D6 = Stop Toggling D0-D7 Valid * D6 stops toggling (The device has completed the Embedded operation.) Figure 6. AC Waveforms for Toggle Bit 1 During Embedded Algorithm Operations AmC0XXDFLKA 21 EMBEDDED ALGORITHMS Start Write Embedded Programming or Erase command sequence to memory segments The Embedded Algorithm operations completely automate the programming and erase procedure by internally executing the algorithmic command sequence of original AMD devices. The devices automatically provide Write Operation Status information with standard read operations. See Table 3 or 4 for Program Command Sequence. Software polling from memory segment Completed 19521D-8 Figure 7. Byte-Wide Programming and Erasure Overview 22 AmC0XXDFLKA EMBEDDED ALGORITHMS Begin Programming Activity Initialization: EF = 0 Initialize Programming Variables: EF = Error Flag EF = 0 = No Programming error EF = 1 = Programming error PGM = Embedded Byte Write Command Sequence Cycle #1-3 (Table 3 or 4) ADRS = Appropriate address for memory segment VDAT = Valid Data PD = Program Data Write PGM Get ADRS/PD VDAT = PD Write ADRS/PGM Write ADRS/VDAT Read ADRS/FMD FMD = Flash Memory Data Yes FMD = VDAT No Begin software polling subroutine (Figure 9) FMD = VDAT Yes No Yes More Data Program Error No Program Complete 19521D-9 Figure 8. Byte-Wide Programming Flow Chart AmC0XXDFLKA 23 EMBEDDED ALGORITHMS Start Subroutine Recommend 8 s time out from previous data polling Read Byte (D0-D7) Addr = VA VA = Byte Address for Programming No = Program time not exceeded limit Yes = Program time exceed limit, device failed Yes D7 = Data? No No D5 = 1? Yes Read Byte (D0-D7) Addr = VA D7 = Data No Yes Device Passed Device failed to program EF = 1 EF = Error Flag Subroutine Return 19521D-10 Note: D7 is checked even if D5 = 1 because D7 may have changed simultaneously with D5 or immediately after D5. Figure 9. Byte-Wide Software Polling for Programming Subroutine 24 AmC0XXDFLKA EMBEDDED ALGORITHMS Begin Erase Activity Initialization: EF = 0 SEG ADRS = 0 ERS = Erase Command Sequence (Even byte per Table 3, Odd byte per Table 4) SEG ADRS = Segment Address = 0 EF = Error Flag = 0 Write ERS Cycle#1-5 Write SEGADRS/ERS Cycle #6 Read SEG ADRS/FMD FMD = Flash Memory Data FFH = Erased Flash Memory Data Yes FMD = FFH No Begin software polling subroutine (Figure 11) FMD = FFH No Yes Increment SEG ADRS Erase Error No Last Segment Address Yes Erase Complete 19521D-11 Figure 10. Byte-Wide Erasure Flow Chart AmC0XXDFLKA 25 EMBEDDED ALGORITHMS Start Subroutine Read Byte (D0-D7) Addr = X D7 = 1 D7 = 1? Yes Yes = Erase Complete No = Erase not Complete No D5 = 1 No D5 = 1? Yes = Erase time exceeded limit, device failed No = Erase time has not exceeded limit X = Don't Care Yes Read Byte (D0-D7) Addr = X D7 = 1 No Yes Device Passed Device failed to program EF = 2 Subroutine Return 19521D-12 Figure 11. Byte-Wide Software Polling Erase Subroutine 26 AmC0XXDFLKA WORD-WIDE PROGRAMMING AND ERASING Word-Wide Programming The word-wide programming sequence will be as usual per Table 5. The Program word command is A0A0H. Each byte is independently programmed. For example, if the high byte of the word indicates the successful completion of programming via one of its write status bits such as D15, software polling should continue to monitor the low byte for write completion and data verification, or vice versa. During the Embedded Programming operations the dev i c e exe c u t e s p r o g r a m m i n g p u l s e s i n 8 s increments. Status reads provide information on the progress of the byte programming relative to the last complete write pulse. Status information is automatically updated upon completion of each internal write pulse. Status information does not change within the 8 s write pulse width. Word-Wide Sector Erasing The word-wide erasing of a memory sector pair is similar to word-wide programming. The erase word command is a 6 bus cycle command sequence per Table 5. Each byte is independently erased and verified. Word-wide erasure reduces total erase time when compared to byte erasure. Each Flash memory device in the card may erase at different rates. Therefore each device (byte) must be verified separately. Start Write Embedded Programming or Erase command sequence to memory segments The Embedded Algorithm operations completely automate the parallel programming and erase procedures by internally executing the algorithmic command sequences of AMD's Flashrite and Flasherase algorithms. The devices automatically provide Write Operation Status information with standard read operations. See Table 5 for Program Command Sequence. Software polling from memory segments Completed 19521D-13 Figure 12. Embedded Algorithm Word-Wide Programming and Erasure Overview AmC0XXDFLKA 27 EMBEDDED ALGORITHMS Begin Programming Activity Initialize Programming Variables: Initialization: EF = 0 PGM =Embedded Word Write Command Sequence Cycle #1-3 (Table 5) EF = Error Flag ADRS = Appropriate address for Memory Segment (Cycle #4) PDW = Program Data Word VWDAT = Valid Word Data EF = Error Flag EF = 0 = No failure EF = 1 = Low byte program error EF = 2 = High byte program error EF = 3 = Word-wide program error Get ADRS/PDW VWDAT = PDW Write PGM Write ADRS/PDW Wait 8 s Read ADRS/FMD FMD = Flash Memory Data Yes FMD = VWDAT No Begin software polling subroutine (Figure 14) FMD = VWDAT Yes No Yes More Data Program Error No Program Complete 19521D-14 Figure 13. Word-Wide Programming Flow Chart 28 AmC0XXDFLKA EMBEDDED ALGORITHMS Begin Subroutine Read Byte (D0-D7) Addr = VA VA = Word Address for Programming Vdata = Valid data D5/13 = 1? D7 = Vdata? Yes No D5 = 1? No Yes = Erase time has exceeded limit, device failed No = Erase time has not exceeded limit Yes Read Byte (D0-D7) Addr = VA D7 = Vdata? Yes No Low byte program time exceeded limit, EF = 1 Read Byte (D8-D15) Addr = VA D15 = Vdata? Yes No D13 = 1? No Yes Read Byte (D8-D15) Addr = VA D15 = Vdata? Yes No High byte program time exceeded limit, EF = 2 + EF Subroutine Return 19521D-15 Figure 14. Word-Wide Software Polling Program Subroutine AmC0XXDFLKA 29 EMBEDDED ALGORITHMS Begin Erase Activity ERS = Segment Erase Command Sequence (Table 5) SEG ADRS = Segment Address EF = Error Flag EF = 0 = No failure EF = 1 = Low byte erase error EF = 2 = High byte erase error EF = 3 = Word-wide erase error Initialization: EF = 0 SEG ADRS = 0 Write ERS Cycle #1-5 Write ERS Cycle #6: SEG ADRS Wait 2 seconds Read SEG ADRS/FMD FMD = Flash Memory Data Yes FMD = FFFFH No Begin software polling subroutine (Figure 16) FMD = FFFFH Yes INC SEG ADRS No Erase Error No Last Segment Address Yes Erase Complete 19521D-16 Figure 15. Word-Wide Erasure Flow Chart 30 AmC0XXDFLKA EMBEDDED ALGORITHMS Begin Subroutine Read Byte (D0-D7) D7 = 1? Yes No D5 = 1? Yes No Read Byte (D0-D7) D7 = 1? No Yes Low byte program time exceeded limit, EF = 1 Read Byte (D8-D15) D15 = 1? Yes No D13 = 1? Yes No D7/15 = 1 Yes = Erase complete No = Erase not complete D5/13 = 1 Read Byte (D8-D15) Yes = Erase time has exceeded limit, device failed No = Erase time has not exceeded limit Yes D15 = 1? No High byte program time exceeded limit, EF = 2 + EF Subroutine Return 19521D-17 Figure 16. Word-Wide Software Polling Erase Subroutine AmC0XXDFLKA 31 ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . -30C to +70C Ambient Temperature with Power Applied. . . . . . . . . . . . . . . . . 0C to +70C Voltage at All Pins (Note 1) . . . . . . . . -0.5 V to +7.0 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . -0.5 V to +6.0 V Output Short Circuit Current (Note 2) . . . . . . . 40 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is VCC + 0.5 V. During voltage transitions, outputs may overshoot to VCC + 2.0 V for periods up to 20ns. 2. No more than one output shorted at a time. Durations of the short circuit should not be greater than one second. Conditions equal VOUT = 0.5 V or 5.0 V, VCC = VCC max. These values are chosen to avoid test problems caused by tester ground degradation. This parameter is sampled and not 100% tested, but guaranteed by characterization. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Case Temperature (TC) . . . . . . . . . . . . . .0C to +70C VCC Supply Voltages . . . . . . . . . . . . +4.75 V to 5.25 V Operating ranges define those limits between which the functionality of the device is guaranteed. 32 AmC0XXDFLKA DC CHARACTERISTICS Byte-Wide Operation Parameter Symbol Parameter Description Test Description 4 MB ILI Input Leakage Current VCC = VCC Max, VIN = VCC or VSS For all cards: CE, REG, WE, RESET 8 MB 20 MB 32 MB 4 MB ILO Output Leakage Current VCC = VCC Max, VOUT = VCC or VSS 8 MB 20 MB 32 MB 4 MB ICCS VCC = VCC Max VCC Standby Current (see note) CE = VCC 0.2 V VIN = VCC or GND 8 MB 20 MB 32 MB ICC1 ICC2 VIL VIH VOL VOH VLKO VCC Active Read Current (see note) VCC Write/Erase Current (see note) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage IOL = 3.2 mA, VCC = VCC Min IOH = 2.0 mA, VCC = VCC Min 3.8 3.2 VCC = VCC Max, CE = VIL, OE = VIH, IOUT = 0 mA, at 3.3 MHz CE = VIL Programming in Progress -0.5 Min Max + 20 + 20 + 20 + 20 20 20 20 20 1.7 1.7 mA 1.7 1.7 45 65 0.8 mA mA V V V V V A A Unit 0.7VCC VCC + 0.3 0.40 VCC 4.2 Note: One Flash device active, all the others in standby. AmC0XXDFLKA 33 Word-Wide Operation Parameter Symbol Parameter Description Test Description 4 MB ILI Input Leakage Current VCC = VCC Max, VIN = VCC or VSS For all cards: CE, REG, WE, RESET 8 MB 20 MB 32 MB 4 MB ILO Output Leakage Current VCC = VCC Max, VOUT = VCC or VSS 8 MB 20 MB 32 MB 4 MB ICCS VCC = VCC Max VCC Standby Current (see note) CE = VCC 0.2 V VIN = VCC or GND 8 MB 20 MB 32 MB ICC1 ICC2 VIL VIH VOL VOH VLKO VCC Active Read Current (see note) VCC Programming Current (see note) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage IOL = 3.2 mA, VCC = VCC Min IOH = 2.0 mA, VCC = VCC Min 3.8 3.2 VCC = VCC Max, CE = VIL, OE = VIH, IOUT = 0 mA, at 3.3 MHz CE = VIL Programming in Progress -0.3 Min Max +20 +20 +20 +20 20 20 20 20 1.7 1.7 mA 1.7 1.7 45 65 0.8 mA mA V V V V V A A Unit 0.7VCC VCC + 0.3 0.40 VCC 4.2 Note: Two Flash devices active, all the others in standby. 34 AmC0XXDFLKA PIN CAPACITANCE Parameter Symbol CIN1 COUT CIN2 CI/O Parameter Description All except A1-A9 Output Capacitance A1-A9 I/O Capacitance D0-D15 Test Conditions VIN = 0 V VOUT = 0 V VIN = 0 V VI/O = 0 V Max 2 2 2 2 Unit pF pF pF pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz. SWITCHING AC CHARACTERISTICS Read Only Operation (Note 1) Card Speed Parameter Symbol JEDEC tAVAV tELQV tAVQV tGLQV tELQX tEHQZ tGLQX tGHQZ tAXQX Standard tRC tCE tACC tOE tLZ tDF tOLZ tDF tOH Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Chip Enable to Output in Low-Z Chip Disable to Output in High-Z Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from First of Address, CE, or OE Change 5 5 75 5 75 Parameter Description -150 ns Unit Min 150 150 150 75 Max ns ns ns ns ns ns ns ns ns Note: 1. Input Rise and Fall Times (10% to 90%): 10 ns, Input Pulse levels: VOL and VOH, Timing Measurement Reference Level: Inputs: VIL and VIH Outputs: VIL and VIH AmC0XXDFLKA 35 AC CHARACTERISTICS Write/Erase/Program Operations Card Speed Parameter Symbol JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tOEH tWHGL tGHWL tELWL tWHEH tWLWH tWHWL tWHWH3 tWHWH4 tVCS tCS tCH tWP tWPH tWR Standard tWC tAS tAH tDS tDH Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Hold Time for Embedded Algorithm Write Recovery Time before Read Read Recovery Time before Write CE Setup Time CE Hold Time Write Pulse Width Write Pulse Width HIGH Embedded Programming Operation (Notes 1, 2, 3) 2 Embedded Erase Operation for each 64K Byte Memory Sector (Notes 1, 2) VCC Setup Time to CE LOW 50 15 Parameter Description Min 150 20 20 50 20 0 6 20 0 20 45 50 8 -150 ns Unit Typ Max ns ns ns ns ns ns s s ns ns ns ns s ms s s Notes: 1. Rise/Fall 10 ns. 2. Maximum specification not needed due to the devices internal stop timer that will stop any erase or write operation that exceed the device specification. 3. Embedded Program Operation of 8 s consist of 6 s program pulse and 2 s write recovery before read. This is the minimum time for one pass through the programming algorithm. D5 = "1" only after a byte takes longer than 2 ms to Write. 36 AmC0XXDFLKA KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State KS000010 SWITCHING WAVEFORMS tRC Addresses tACC Addresses Stable CE tOE OE (tDF) tOE WE (tCE) (tOH) High-Z High-Z Outputs Output Valid 19521D-18 Note: CE refers to CE1 and CE2. Figure 17. AC Waveforms for Read Operations AmC0XXDFLKA 37 SWITCHING WAVEFORMS tAH Addresses XXXXH tAS CE tGHWL OE tWP tWP WE tWPH tCS Data tDS VCC tVCS 19521D-19 XXXXH XXXXH XXXXH XXXXH SA tDH AAH 55H 80H AAH 55H 10H/30H Note: SA is the sector address for Sector Erase per Table 6. Figure 18. AC Waveforms Segment/Sector Byte Erase Operations 38 AmC0XXDFLKA SWITCHING WAVEFORMS Data Polling Addresses XXXXH tWC CE tGHWL OE tWP WE tCS tWPH tDH Data tDS VCC A0H PD D7 DOUT tOH tCE 19521D-20 PA tAH tAS PA tRC tWHWH3 tOE tDF tVCS Notes: 1. Figure indicates last two bus cycles of four bus cycle sequence. 2. PA is address of the memory location to be programmed. 3. PD is data to be programmed at byte address. 4. D7 is the output of the complement of the data written to the device. 5. DOUT is the output of the data written to the device. Figure 19. AC Waveforms for Byte Write Operations AmC0XXDFLKA 39 AC CHARACTERISTICS--ALTERNATE CE CONTROLLED WRITES Write/Erase/Program Operations Card Speed Parameter Symbol JEDEC tAVAV tAVEL tELAX tDVEH tEHDX tGLDV tGHEL tWLEL tEHWH tELEH tEHEL tEHEH3 tEHEH4 tVCS tWS tWH tCP tCPH Standard tWC tAS tAH tDS tDH tOE Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Hold Time for Embedded Algorithm Read Recovery Time before Write WE Setup Time before CE WE Hold Time CE Pulse Width CE Pulse Width HIGH (Note 3) Embedded Programming Operation (Notes 3, 4) 2 Embedded Erase Operation for each 64K byte Memory Sector (Notes 1, 2) VCC Setup Time to Write Enable LOW 50 Parameter Description -150 ns Min 150 20 55 50 20 20 20 0 0 80 50 8 Max Unit ns ns ns ns ns ns ns ns ns ns ns s ms s ms Notes: 1. Rise/Fall 10 ns. 2. Maximum specification not needed due to the internal stop timer that will stop any erase or write operation that exceed the device specification. 3. Card Enable Controlled Programming: Flash Programming is controlled by the valid combination of the Card Enable (CE1, CE2) and Write Enable (WE) signals. For systems that use the Card Enable signal(s) to define the write pulse width, all Setup, Hold, and inactive Write Enable timing should be measured relative to the Card Enable signal(s). 4. Embedded Program Operation of 8 s consist of 6 s program pulse and 2 s write recovery before read. This is the minimum time for one pass through the programming algorithm. D5 = "1" only after a byte takes longer than 2 ms to Write. 40 AmC0XXDFLKA SWITCHING WAVEFORMS Data Polling Addresses XXXXH tWC WE tGHEL OE tWH tCP CE tWS Data tDS tCPH tDH A0H PD D7 DOUT tWHWH3 or 4 PA tAS tAH PA VCC tVCS 19521D-21 Notes: 1. Figure indicates last two bus cycles of four bus cycle sequence. 2. PA is address of the memory location to be programmed. 3. PD is data to be programmed at byte address. 4. D7 is the output of the complement of the data written to the device. 5. DOUT is the output of the data written to the device. Figure 20. Alternate CE Controlled Byte Write Operation Timings CE The rising edge of the last WE signal WE Entire programming or erase operations RY/BY tBUSY 19521D-22 Figure 21. RY/BY Timing Diagram During Program/Erase Operations AmC0XXDFLKA 41 RESET tRP tReady RY/BY 19521D-23 Figure 22. RESET Timing Diagram Enter Embedded Erasing WE Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read D6 D2 Toggle D2 and D6 with OE 19521D-24 Note: D2 is read from the erase suspended sector. Figure 23. D2 vs. D6 42 AmC0XXDFLKA CARD INFORMATION STRUCTURE The D-Series card contains a separate EEPROM memory for the Card Information Structure (CIS). This allows all of the Flash memory to be used for the common memory space. Part of the common memory space could also be used to sore the CIS. The EEPROM used in the D-Series card is designed to operate from a 5 V single power supply. Table 9 shows the CIS information stored in the AMD Flash memory card. transitions. The AMD PC Card will power-up into a READ mode when VCC is greater than VLKO of 3.2 V. Erasing of memory sectors or memory segments can be accomplished only by writing the proper Erase command to the card along with the proper Chip Enable, Output Enable and Write Enable control signals. Hot insertion of PC cards is not permitted by the PCMCIA standard. SYSTEM DESIGN AND INTERFACE INFORMATION Power Up and Power Down Protection AMD's Flash memory devices are designed to protect against accidental programming or erasure caused by spurious system signals that might exist during power Note: Hot insertion is defined as the socket condition where the card is inserted or removed with any or all of the following conditions present: VCC = VCCH, VPP =VPPH, address and/or data lines are active. System Power Supply Decoupling The AMD Flash memory card has a 0.1 F decoupling capacitor between the VCC and the GND pins. It is recommended the system side also have a 4.7 F capacitor between the VCC and the GND pins. AmC0XXDFLKA 43 Table 9. Tuple Address 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah : : 6Ah 6Ch 2 Mbyte Card Tuple Value 01h 03h 53h 0Eh FFh 18h 03h 01h 3Dh FFh 1Eh 07h 02h 11h 01h 01h 01h 01h FFh 15h 03h 04h 01h FFh 17h 04h 47h 3Ah 00h FFh 80h 05h 41h 4Dh 44h 00h FFh 81h xxh xxh xxh FFh AMD's CIS for D-Series Cards Tuples and Remarks CISTPL_DEVICE [Common Memory] TPL_LINK Flash Device, Card Speed: 53h = 150 ns (52h for 200 ns) Card Size: 0Eh = 4 MB, 1Eh = 8 MB, 4Eh = 20 MB, 7Eh = 32 MB (Note 1) End of Tuple CISTPL_JEDEC [Common Memory] TPL_LINK AMD MFG ID Code Device ID Code: 3Dh = 16 Mbit Device, Am29F016C End of Tuple CISTPL_DEVICEGEO TPL_LINK no FFh terminator DGTPL_BUS: Bus Width DGTPL_EBS: 11h = 64K Byte Erase Block size DGTPL_RBS: Read Byte Size DGTPL_WBS: Write Byte Size DGTPL_PART: Number of partition FL DEVICE INTERLEAVE: No interleave End of Tuple CISTPL_VERS1 TPL_LINK Major version number 1 Minor version for PCMCIA Std. 2.0 End of Tuple CISTPL_DEVICE_A [Attribute Memory] TPL_LINK EEPROM with extended speed Extended speed = 250 ns Device Size = 1 unit of 512 byte End of Tuple Vendor-Specific Tuple TPL_LINK "A" "M" "D" END TEXT End of Tuple Vendor Specific Tuples: 81h ASCII Characters : ASCII Characters CISTPL_END Note: See PCMCIA specifications for parsing and card size values. 44 AmC0XXDFLKA PHYSICAL DIMENSIONS Type 1 PC Card 85.6 0.2 mm 10.0 Min (mm) 54.0 0.1 mm 10.0 Min (mm) 3.3 0.1 mm Front Side 1 35 Back Side 34 68 Trademarks Copyright (c) 1996 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. AmC0XXDFLKA 45 REVISION SUMMARY FOR AMC0XXDFLKA Global Added 32 MByte Card availability. Deleted 200 ns speed option. Block Diagram Updated schematic to show correct number of flash devices for 32 MByte card. Pin Description A24-A0 should all be driven. Memory Card Operations Simplified description of erase operations. Table 1, Common Memory Bus Operations Simplified bus operation table. Table 2, Attribute Memory Bus Operations Simplified attribute memory bus operation table. Absolute Maximum Ratings & Operating Ranges Increased operating & maximum temperature range to +70C DC Characteristics Revised VIH to 0.7 VCC AC Characteristics Removed 200 ns timing characteristics Table 9, AMD CIS for D-Series Cards Corrected CIS values for card density 46 AmC0XXDFLKA |
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